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ltc4441/ltc4441-1 1 44411fa typical a pplica t ion fea t ures descrip t ion n-channel mosfet gate driver the ltc ? 4441/ltc4441-1 is an n-channel mosfet gate driver that can supply up to 6a of peak output current. the chip is designed to operate with a supply voltage of up to 25v and has an adjustable linear regulator for the gate drive. the gate drive voltage can be programmed between 5v and 8v. the ltc4441/ltc4441-1 features a logic threshold driver input. this input can be driven below ground or above the driver supply. a dual function control input is provided to disable the driver or to force the chip into shutdown mode with <12a of supply current. undervoltage lockout and overtemperature protection circuits will disable the driver output when activated. the ltc4441 also comes with an open-drain output that provides adjustable leading edge blanking to prevent ringing when sensing the source cur - rent of the power mosfets. the ltc4441 is available in a thermally enhanced 10-lead msop package. the ltc4441-1 is the so-8 version without the blanking function. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6677210. rise/fall time vs c load a pplica t ions n 6a peak output current n wide v in supply range: 5v to 25v n adjustable gate drive voltage: 5v to 8v n logic input can be driven below ground n 30ns propagation delay n supply independent cmos/ttl input thresholds n undervoltage lockout n low shutdown current: <12a n overtemperature protection n adjustable blanking time for mosfet s current sense signal (ltc4441) n available in so-8 and 10-lead msop (exposed pad) packages n power supplies n motor/relay control n line drivers n charge pumps + fb r2 86.6k r6 r3 5m r9 8.06k 4441 ta01a r8 511k r7 r1 330k r5 shutdown v in 6v to 24v sgnd c vcc 10f x5r l1 10h 20a d1 mbr10100 si7370 2 22f 25v x7r + c out v out 52v 2a en/shdn ltc4441 v in rblank in drv cc out pgnd blank r4 100 q2 ltc3803 switching controller gate sense + gnd fb c load (nf) 0 155 10 20 25 30 35 4540 50 rise/fall time (ns) 4441 ta01b 200 180 80 60 20 40 0 160 140 120 100 t a = 25c drv cc = 5v rise time fall time
ltc4441/ltc4441-1 2 44411fa a bsolu t e maxi m u m r a t ings supply voltage v in ............................................................................ 28v dr v cc ......................................................................... 9v in put voltage in ............................................................. C15 v to 15v fb, en/ shdn .......................... C 0.3v to drv cc + 0.3v rblank, blank (ltc4441 only) ............ C0.3v to 5v (notes 1, 8) 1 2 3 4 5 pgnd blank rblank sgnd in 10 9 8 7 6 out drv cc v in fb en/shdn top view 11 mse package 10-lead plastic msop t jmax = 125c, ja = 38c/w (note 3) exposed pad (pin 11) is gnd, must be soldered to pcb 1 2 3 4 8 7 6 5 top view out drv cc v in fb pgnd sgnd in en/shdn s8 package 8-lead plastic so t jmax = 125c, ja = 150c/w p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc4441emse#pbf ltc4441emse#trpbf ltbjq 10-lead plastic msop C40c to 125c ltc4441imse#pbf ltc4441imse#trpbf ltbjp 10-lead plastic msop C40c to 125c ltc4441mpmse#pbf ltc4441mpmse#trpbf ltbjp 10-lead plastic msop C55c to 125c ltc4441es8-1#pbf ltc4441es8-1#trpbf 44411 8-lead plastic so C40c to 125c ltc4441is8-1#pbf ltc4441is8-1#trpbf 4441i1 8-lead plastic so C40c to 125c lead based finish tape and reel part marking* package description temperature range ltc4441emse ltc4441emse#tr ltbjq 10-lead plastic msop C40c to 125c ltc4441imse ltc4441imse#tr ltbjp 10-lead plastic msop C40c to 125c ltc4441mpmse ltc4441mpmse#tr ltbjp 10-lead plastic msop C55c to 125c ltc4441es8-1 ltc4441es8-1#tr 44411 8-lead plastic so C40c to 125c ltc4441is8-1 ltc4441is8-1#tr 4441i1 8-lead plastic so C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ out output current ............................................ 100 ma operating junction temperature range (note 2) .................................................. C 55c to 125c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) .................. 3 00c
ltc4441/ltc4441-1 3 44411fa e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc4441/ltc4441-1 are tested under pulsed load conditions such that t j t a . the ltc4441e/ltc4441e-1 are guaranteed to meet performance specifications from 0c to 85c operating junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design characterization and correlation with statistical process controls. the ltc4441i/ltc4441i-1 grade are the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 7.5v, drv cc = 5v, unless otherwise specified. symbol parameter conditions min typ max units v drvcc driver supply programmable range l 5 8 v i vin v in supply current en/shdn = 0v, in = 0v en/shdn = 5v, in = 0v f in = 100khz, c out = 4.7nf (note 4) l l 5 250 3 12 500 6 a a ma drv cc regulator v fb regulator feedback voltage v in = 7.5v l 1.11 1.21 1.31 v v drvcc(line) regulator line regulation v in = 7.5v to 25v 9 40 mv v drvcc(load) load regulation load = 0ma to 40ma C0.1 % v dropout regulator dropout voltage load = 40ma 370 mv v uvlo fb pin uvlo voltage rising edge falling edge 1.09 0.97 v v input v ih in pin high input threshold rising edge l 2 2.4 2.8 v v il in pin low input threshold falling edge l 1 1.4 1.8 v v ih -v il in pin input voltage hysteresis rising-falling edge 1 v i inp in pin input current v in = 10v l 0.01 10 a i en/shdn en/shdn pin input current v en/shdn = 9v l 0.01 1 a v shdn en/ shdn pin shutdown threshold falling edge 0.45 v v en en/shdn pin enable threshold rising edge falling edge l 1.036 1.21 1.09 1.145 v v v en(hyst) en/shdn pin enable hysteresis rising-falling edge 0.12 v output r onl driver output pull-down resistance i out = 100ma l 0.35 0.8 i pu driver output peak pull-up current drv cc = 8v 6 a i pd driver output peak pull-down current drv cc = 8v 6 a r on(blank) blank pin pull-down resistance in = 0v, i blank = 100ma ltc4441 only 11 v rblank rblank pin voltage rblank = 200k ltc4441 only 1.3 v switching timing t phl driver output high-low propagation delay c out = 4.7nf (note 5) 30 ns t plh driver output low-high propagation delay c out = 4.7nf (note 5) 36 ns t r driver output rise time c out = 4.7nf (note 5) 13 ns t f driver output fall time c out = 4.7nf (note 5) 8 ns t blank driver output high to blank pin high rblank = 200k (note 6) 200 ns guaranteed over the C40c to 125c operating junction temperature range. the ltc4441mp is guaranteed and tested over the full C55c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance.
ltc4441/ltc4441-1 4 44411fa in pin low threshold voltage vs temperature in pin high threshold voltage vs temperature en pin input threshold voltage vs temperature temperature (c) ?75 ?50 in pin input threshold (v) 25 4441 g01 ?25 0 50 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 75 100 125 v in = 7.5v drv cc = 5v temperature (c) ?75 ?50 in pin input threshold (v) 25 4441 g02 ?25 0 50 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 75 100 125 v in = 7.5v drv cc = 5v temperature (c) ?75 ?50 en pin input threshold voltage (v) 25 4441 g03 ?25 0 50 1.30 1.24 1.22 1.28 1.26 1.20 1.18 1.14 1.10 1.06 1.16 1.12 1.08 1.04 75 100 125 v in = 7.5v drv cc = 5v rising edge falling edge fb pin uvlo threshold vs temperature sd pin input threshold voltage vs temperature drv cc voltage vs temperature temperature (c) ?75 ?50 fb pin uvlo threshold voltage (v) 25 4441 g04 ?25 0 50 1.20 1.00 0.96 0.88 0.92 1.16 1.12 1.08 0.84 1.04 75 100 125 v in = 7.5v rising edge falling edge temperature (c) ?75 ?50 sd pin input threshold voltage (v) 25 4441 g05 ?25 0 50 0.80 0.50 0.45 0.35 0.40 0.75 0.70 0.65 0.60 0.30 0.55 75 100 125 rising edge falling edge v in = 7.5v drv cc = 5v temperature (c) ?75 ?50 drv cc voltage (v) 25 4441 g06 ?25 0 50 5.50 5.20 5.15 5.05 5.10 5.45 5.40 5.35 5.30 5.00 5.25 75 100 125 r1 = 330k r2 = 100k v in = 25v v in = 7.5v e lec t rical c harac t eris t ics note 3: failure to solder the exposed pad of the mse package to the pc board will result in a thermal resistance much higher than 38c/w. note 4: supply current in normal operation is dominated by the current needed to charge and discharge the external power mosfet gate. this current will vary with supply voltage, switching frequency and the external mosfets used. note 5: rise and fall times are measured using 10% and 90% levels. delay times are measured from 50% of input to 20%/80% levels at driver output. note 6: blanking time is measured from 50% of out leading edge to 10% of blank with a 1k pull-up at blank pin. ltc4441 only. note 7: guaranteed by design, not subject to test. note 8: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the maximum operating junction temperature may impair device reliability. typical p er f or m ance c harac t eris t ics
ltc4441/ltc4441-1 5 44411fa typical p er f or m ance c harac t eris t ics drv cc load regulation drv cc line regulation drv cc dropout voltage vs temperature i load (ma) 0 drv cc (v) 60 4441 g07 20 40 80 5.50 5.20 5.15 5.05 5.10 5.45 5.40 5.35 5.30 5.00 5.25 100 120 140 160 180 200 v in = 7.5v t a = 25c r1 = 330k r2 = 100k v in (v) 0 drv cc (v) 4441 g08 5.30 5.20 5.15 5.05 5.10 5.00 5.25 5 10 15 20 25 30 t a = 25c r1 = 330k r2 = 100k temperature (c) ?75 ?50 drv cc dropout voltage (mv) 25 4441 g09 ?25 0 50 1000 400 300 100 200 900 800 700 600 0 500 75 100 125 v in = 7.5v drv cc = 5v i load = 40ma out pin pull-down resistance vs temperature t plh , t phl vs drv cc t plh , t phl vs temperature t plh , t phl vs c load rise/fall time vs drv cc rise/fall time vs temperature temperature (c) ?75 ?50 out pin pull-down resistance () 25 4441 g10 ?25 0 50 0.8 0.4 0.3 0.1 0.2 0.7 0.6 0 0.5 75 100 125 v in = 7.5v drv cc = 5v drv cc (v) 4.5 t plh , t phl (ns) 6.0 4441 g11 5.0 5.5 6.5 60 40 30 10 20 0 50 7.0 7.5 8.0 8.5 9.0 t a = 25c c load = 4.7nf t phl t plh temperature (c) ?75 ?50 25 ?25 0 50 75 100 125 t plh , t phl (ns) 4441 g12 60 40 30 10 20 0 50 v drvcc = 5v c load = 4.7nf t phl t plh c load (nf) 0 155 10 20 25 30 35 4540 50 t plh , t phl (ns) 4441 g13 100 90 40 30 10 20 0 80 70 60 50 t a = 25c drv cc = 5v t phl t plh drv cc (v) 4.5 rise/fall time (ns) 6.0 4441 g14 5.0 5.5 6.5 30 20 15 5 10 0 25 7.0 7.5 8.0 8.5 9.0 t a = 25c c load = 4.7nf rise time fall time rise/fall time (ns) 4441 g15 30 20 15 5 10 0 25 v drvcc = 5v c load = 4.7nf rise time fall time temperature (c) ?50 25 ?25 0 50 75 100 125
ltc4441/ltc4441-1 6 44411fa typical p er f or m ance c harac t eris t ics rise/fall time vs c load blanking time vs r blank blanking time vs temperature c load (nf) 0 155 10 20 25 30 35 4540 50 rise/fall time (ns) 4441 g16 200 180 80 60 20 40 0 160 140 120 100 t a = 25c drv cc = 5v rise time fall time r blank (k) 0 blanking time (ns) 300 4441 g17 100 200 400 500 200 150 50 100 450 400 350 300 0 250 500 600 700 t a = 25c drv cc = 5v ltc4441 blanking time (ns) 4441 g18 250 190 180 160 170 240 230 220 210 150 200 temperature (c) ?75 ?50 25 ?25 0 50 75 100 125 v in = 7.5v drv cc = 5v ltc4441 v in operating supply current vs temperature v in standby supply current vs temperature temperature (c) ?75 ?50 v in supply current (a) 25 4441 g19 ?25 0 50 500 200 150 50 100 450 400 350 300 0 250 75 100 125 en = 5v in = 0v v in = 7.5v v in = 25v temperature (c) ?75 ?50 v in supply current (a) 25 4441 g20 ?25 0 50 15 7 6 4 5 13 11 14 12 10 9 0 1 2 3 8 75 100 125 en = 0v in = 0v v in = 7.5v v in = 25v i vin vs f in i vin vs c load f in (khz) 0 300 100 200 400 500 600 700 900800 1000 i vin (ma) 4441 g21 50 45 20 15 5 10 0 40 35 30 25 t a = 25c c load = 4.7nf drv cc = 5v drv cc = 9v c load (nf) 0 155 10 20 25 30 35 4540 50 i vin (ma) 4441 g22 60 50 20 10 0 40 30 t a = 25c f in = 100khz drv cc = 5v drv cc = 9v
ltc4441/ltc4441-1 7 44411fa p in func t ions pgnd (pin 1/pin 1): driver ground. connect the drv cc bypass capacitor directly to this pin, as close as possible to the ic. in addition, connect the pgnd and sgnd pins together close to the ic, and then connect this node to the source of the power mosfet (or current sense resistor) with as short and wide a pcb trace as possible. blank (pin 2/na): current sense blanking output. use this pin to assert a blanking time in the power mosfets source current sense signal. the ltc4441 pulls this open- drain output to sgnd if the driver output is low. the output becomes high impedance after a programmable blanking time from the driver leading edge output. this blanking time can be adjusted with the rblank pin.* rblank (pin 3/na): blanking time adjust input. connect a resistor from this pin to sgnd to set the blanking time. a small resistor value gives a shorter delay. leave this pin floating if the blank pin is not used.* sgnd (pin 4/pin 2): signal ground. ground return for the drv cc regulator and low power circuitry. in (pin 5/pin 3): driver logic input. this is the noninverting driver input under normal operating conditions. en/shdn (pin 6/pin 4): enable/shutdown input. pulling this pin above 1.21v allows the driver to switch. pulling this pin below 1.09v forces the driver output to go low. pulling this pin below 0.45v forces the ltc4441/ltc4441-1 into shutdown mode; the drv cc regulator turns off and the supply current drops below 12a. fb (pin 7/pin 5): drv cc regulator feedback input. connect this pin to the center tap of an external resistive divider between drv cc and sgnd to program the drv cc regulator output voltage. to ensure loop stability, use the value of 330k for the top resistor, r1. v in (pin 8/pin 6): main supply input. this pin powers the drv cc linear regulator. bypass this pin to sgnd with a 1f ceramic, tantalum or other low esr capacitor in close proximity to the ltc4441/ltc4441-1. drv cc (pin 9/pin 7): linear regulator output. this output pin powers the driver and the control circuitry. bypass this pin to pgnd using a 10f ceramic, low esr (x5r or x7r) capacitor in close proximity to the ltc4441/ltc4441-1. out (pin 10/pin 8): driver output. gnd (exposed pad pin 11/na): ground. the exposed pad must be soldered to the pcb ground. (msop/so-8) *available only on the 10-lead version of the ltc4441.
ltc4441/ltc4441-1 8 44411fa b lock diagra m 1.09v in 1.21v ? + uvlo reg en inb 1.21v 0.45v shutdown fb v in en/shdn sgnd shdn thermal shutdown bias leading edge delay q1 p1 m reg drv cc out pgnd rblank blank 4441 bd n1 mb for 10-lead ltc4441 only
ltc4441/ltc4441-1 9 44411fa a pplica t ions i n f or m a t ion overview power mosfets generally account for the majority of power lost in a converter. it is important to choose not only the type of mosfet used, but also its gate drive circuitry. the ltc4441/ltc4441-1 is designed to drive an n-channel power mosfet with little efficiency loss. the ltc4441/ ltc4441-1 can deliver up to 6a of peak current using a combined npn bipolar and mosfet output stage. this helps to turn the power mosfet fully on or off with a very brief transition region. the ltc4441/ltc4441-1 includes a programmable linear - regulator to regulate the gate drive voltage. this regulator provides the flexibility to use either standard threshold or logic level mosfets. drv cc regulator an internal, p-channel low dropout linear regulator provides the drv cc supply to power the driver and the pre-driver logic circuitry as shown in figure 1. the regulator output voltage can be programmed between 5v and 8v with an external resistive divider between drv cc and sgnd and a center tap connected to the fb pin. the regulator needs an r1 value of around 330k to ensure loop stability; the value of r2 can be varied to achieve the required drv cc voltage: r2 = 406k drv cc ? 1.21v the drv cc regulator can supply up to 100ma and is short-circuit protected. the output must be bypassed to the pgnd pin in very close proximity to the ic pins with a minimum of 10f ceramic, low esr (x5r or x7r) capacitor. good bypassing is necessary as high transient supply currents are required by the driver. if the input supply voltage, v in , is close to the required gate drive voltage, this regulator can be disabled by connecting the drv cc and fb pins to v in . the ltc4441/ltc4441-1 monitors the fb pin for drv cc s uvlo condition (uvlo in figure 1). during power-up, the driver output is held low until the drv cc voltage reaches 90% of the programmed value. thereafter, if the drv cc voltage drops more than 20% below the programmed value, the driver output is forced low. logic input stage the ltc4441/ltc4441-1 driver employs ttl/cmos com- patible input thresholds that allow a low voltage digital signal to drive standard power mosfets. the ltc4441/ ltc4441-1 contains an internal voltage regulator that biases the input buffer, allowing the input thresholds (v ih = 2.4v, v il = 1.4v) to be independent of the programmed- driver supply, drv cc , or the input supply, v in . the 1v hysteresis between v ih and v il eliminates false triggering due to noise during switching transitions. however, care should be taken to isolate this pin from any noise pickup, especially in high frequency, high voltage applications.the ltc4441/ltc4441-1 input buffer has high input impedance and draws negligible input current, simplifying the drive circuitry required for the input. this input can withstand voltages up to 15v above and below ground. this makes the chip more tolerant to ringing on the input digital signal caused by parasitic inductance. 1.09v out c vcc 4441 f01 1.21v uvlo driver enable driver m reg fb r2 r1 330k ? + v in drv cc pgnd reg ltc4441 figure 1. drv cc regulator
ltc4441/ltc4441-1 10 44411fa driver output stage a simplified version of the ltc4441/ltc4441-1s driver - output stage is shown in figure 2. the pre-driver that drives q1, p1 and n1 uses an adap- tive method to minimize cross-conduction currents. this is done with a 5ns nonoverlapping transition time. n1 is fully turned off before q1 is turned on and vice-versa using this 5ns buffer time. this minimizes any cross-conduction currents while q1 and n1 are switching on and off without affecting their rise and fall times. thermal shutdown the ltc4441/ltc4441-1 has a thermal detector that dis - ables the drv cc regulator and pulls the driver output low when activated. if the junction temperature exceeds150c, the driver pull-up devices, q1 and p1, turn off while the pull-down device, n1, turns on briskly for 200ns to quickly pull the output low. the thermal shutdown circuit has 20c of hysteresis. enable/shutdown input the en/ shdn pin serves two functions. pulling this pin below 0.45v forces the ltc4441/ltc4441-1 into shutdown mode. in shutdown mode, the internal circuitry and the drv cc regulator are off and the supply current drops to <12a. if the input voltage is between 0.45v and 1.21v, the drv cc regulator and internal circuit power up but the driver output stays low. if the input goes above 1.21v, the driver starts switching according to the input logic signal. the driver enable comparator has a small hysteresis of 120mv. blanking in some switcher applications, a current sense resistor is placed between the low side power mosfets source terminal and ground to sense the current in the mosfet. with this configuration, the switching controller must incorporate some timing interval to blank the ringing onthe current sense signal immediately after the mosfet is turned on. this ringing is caused by the parasitic induc- tance and capacitance of the pcb trace and the mosfet. the duration of the ringing is thus dependent on the pcb layout and the components used and can be longer than the blanking interval provided by the controller. a pplica t ions i n f or m a t ion q1 p1 drv cc n1 n3 drv cc ltc4441 pgnd out c gd v in power mosfet 4441 f02 load inductor c gs n2 r o figure 2. driver output stage the pull-up device is the combination of an npn transis- tor, q1, and a p-channel mosfet, p1. this provides both the ability to swing to rail (drv cc ) and deliver large peak charging currents. the pull-down device is an n-channel mosfet, n1, with a typical on resistance of 0.35. the low impedance of n1 provides fast turn-off of the external power mosfet and holds the power mosfets gate low when its drain voltage switches. when the power mosfets gate is pulled low (gate shorted to source through n1) by the ltc4441/ ltc4441-1, its drain voltage is pulled high by its load (e.g., inductor or resistor). the slew rate of the drain voltage causes current to flow to the mosfets gate through its gate-to-drain capacitance. if the mosfet driver does not have sufficient sink current capability (low output imped- ance), the current through the power mosfets c gd can momentarily pull the gate high and turn the mosfet back on. a similar situation occurs during power-up when v in is- ramping up with the drv cc regulator output still low. n1 is off and the driver output, out, may momentarily pull high through the power mosfets c gd , turning on the power mosfet. the n-channel mosfets n2 and n3,shown in figure 2, prevent the driver output from going high in this situation. if drv cc is low, n3 is off. if out is pulled high through the power mosfets c gd , the gate of n2 gets pulled high through ro. this turns n2 on, which then pulls out low. once drv cc is >1v, n3 turns on to hold the n2 gate low, thus disabling n2.
ltc4441/ltc4441-1 11 44411fa the 10-lead ltc4441 includes an open-drain output that can be used to extend this blanking interval. the 8-lead ltc4441-1 does not have this blanking function. figure 3 shows the blank pin connection. the blank pin is con- nected directly to the switching controllers sense + input. figure 4 shows the blanking waveforms. if the driver input is low, the external power mosfet is off and mb turns on to hold sense + low. if the driver input goes high, the power mosfet turns on after the drivers propagation delay. mb remains on, attenuating the ringing seen by the controllers sense + input. after the programmed blanking time, mb turns off to enable the current sense signal. mb is designed to turn on and turn off at a controlled slew rate. this is to prevent the gate switching noise from coupling into the current sense signal. a pplica t ions i n f or m a t ion power dissipation to ensure proper operation and long-term reliability, the ltc4441/ltc4441-1 must not operate beyond its maxi - mum temperature rating. the junction temperature can be calculated by: i q(tot) = i q + ? ? q g p d = v in ? (i q + ? ? q g ) t j = t a + p d ? ja where: i q = ltc4441/ltc4441-1 static quiescent current, typically 250a ? = logic input switching frequency q g = power mosfet total gate charge at corre- sponding v gs voltage equal to drv cc v in = ltc4441/ltc4441-1 input supply voltage t j = junction temperature t a = ambient temperature ja = junction-to-ambient thermal resistance. the 10-pin msop package has a thermal resistance of ja = 38c/w. blank sgnd rblank power mosfet load inductor to switching controller?s current sense input out ltc4441 r4 v in r3 4441 f03 sense + sense ? keep this trace short mb driver leading edge delay r7 pgnd figure 3. blanking circuit figure 4. blanking waveforms blanking time in out mb gate blank/sense + 4441 f04 power mosfet?s current power mosfet?s source terminal the blanking interval can be adjusted using resistor r7 connected to the rblank pin. a small resistance value gives a shorter interval with a default minimum of 75ns. the value of the resistor r4 and the on-resistance of mb (typically 11) form a resistive divider attenuating the ringing. r4 needs to be large for effective blanking, but not so large as to cause delay to the sense signal. a resistance value of 1k to 10k is recommended. for optimum performance, the ltc4441/ltc4441-1should be placed as close as possible to the powermosfet and current sense resistor, r3.
ltc4441/ltc4441-1 12 44411fa a pplica t ions i n f or m a t ion the total supply current, i q(tot) , consists of the ltc4441/ ltc4441-1s static quiescent current, i q , and the current required to drive the gate of the power mosfet, with thelatter usually much higher than the former. the dissi - pated power, p d , includes the efficiency loss of the drv cc regulator. with a programmed drv cc , a high v in results in higher efficiency loss. as an example, consider an application with v in = 12v. the switching frequency is 300khz and the maximum ambient temperature is 70c. the power mosfet chosen is three pieces of irfb31n20d, which has a maximum r ds(on) of 82m (at room temperature) and a typical total gatecharge of 70nc (the temperature coefficient of the gate charge is low). i q(tot) = 500a + 210nc ? 300khz = 63.5ma p ic = 12v ? 63.5ma = 0.762w t j = 70c + 38c/w ? 0.762w = 99c this demonstrates how significant the gate charge cur - rent can be when compared to the ltc4441/ltc4441-1s static quiescent current. to prevent the maximum junc - tion temperature from being exceeded, the input supply current must be checked when switching at high v in . a tradeoff between the operating frequency and the size of the power mosfet may be necessary to maintain areliable ltc4441/ltc4441-1 junction temperature. prior to lower - ing the operating frequency, however, be sure to check with power mosfet manufacturers for their innovations on low q g , low r ds(on) devices. power mosfet manufacturing technologies are continually improving, with newer and better performing devices being introduced. pc board layout checklist when laying out the printed circuit board, the following - checklist should be used to ensure proper operation of the ltc4441/ltc4441-1: a. mount the bypass capacitors as close as possible be- tween the dr v cc and pgnd pins and between the v in and sgnd pins. the pcb trace loop areas should be tightened as much as possible to reduce inductance. b. use a low inductance, low impedance ground plane to reduce any ground drop. remember that the ltc4441/ l tc4441-1 switches 6a peak current and any significant ground drop will degrade signal integrity. c. keep the pcb ground trace between the ltc4441/ l tc4441-1 ground pins (pgnd and sgnd) and the external current sense resistor as short and wide as possible. d. plan the ground routing carefully. know where the large load switching current paths are. maintain separate ground return paths for the input pin and output pin to avoid sharing small-signal ground with large load ground return. t erminate these two ground traces only at the gnd pin of the driver (star network). e. keep the copper trace between the driver output pin andthe load short and wide. f. place the small-signal components away from the high frequency switching nodes. these components include the resistive networks connected to the fb, rblank and en/shdn pins.
ltc4441/ltc4441-1 13 44411fa p ackage descrip t ion mse package 10-lead plastic msop (reference ltc dwg # 05-08-1664 rev g) msop (mse) 0910 rev g 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ? 0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does not include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc 0.305 0.038 (.0120 .0015) typ bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref
ltc4441/ltc4441-1 14 44411fa p ackage descrip t ion s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0? 8 typ .008 ? .010 (0.203 ? 0.254) so8 0303 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
ltc4441/ltc4441-1 15 44411fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 03/11 added mp-grade part. changes reflected throughout the data sheet. 1-16
ltc4441/ltc4441-1 16 44411fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2004 lt 0311 rev a ? printed in usa r ela t e d p ar t s part number description comments ltc4440/ LTC4440-5 high voltage, high speed, high side n-channel gate driver up to 80v supply voltage, 8v v cc 15v, 2.4a peak pull-up/1.5? peak pull-down ltc4442 high speed synchronous n-channel mosfet driver up to 38v supply voltage, 6v v cc 9.5v ltc4449 high speed synchronous n-channel mosfet driver up to 38v supply voltage, 4.5v v cc 6.5v ltc4444/ ltc4444-5 high voltage synchronous n-channel mosfet driver with shoot thru protection up to 100v supply voltage, 4.5v/7.2v v cc 13.5v, 3a peak pull-up/0.55? peak pull-down ltc4446 high voltage synchronous n-channel mosfet driver without shoot thru protection up to 100v supply voltage, 7.2v v cc 13.5v, 3a peak pull-up/0.55? peak pull-down ltc1154 high side micropower mosfet driver up to 18v supply voltage, 85a quiescent current, internal charge pump

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